The present invention relates to the design of integrated circuits (ICs), and more specifically, to placement analysis of such circuits.
In VLSI (very large scale integration) digital design, a netlist (from logic synthesis) includes a network of combinational logic gates and memory elements such as latches/flip-flops. The placement stage determines the locations of all modules in the netlist (modules and their interconnect(s)), generated from logic synthesis. Typically, the primary objective of placement is to optimize wire length, subject to the constraint of no overlap(s) between modules. If the placement stage is unstable, it can generate very different placements even with minor changes in the netlist (e.g., netlist reordering, module insertion, fanout optimization, etc.).
To estimate the final routed wire length, the Half-Perimeter Wire Length (HPWL, or bounding box model) is commonly used and optimized during placement, mainly due to its accuracy and efficiency. Modern HPWL-driven analytical placement exhibits instability with the change of design/netlist.